®Sypher AES-256-bit Encryption FPGA Module
Caveat: None
Certificate
| Certificate number | 3201 |
|---|---|
| Standard | FIPS 140-2 |
| Status | historical |
| Overall level | 1 |
| Module type | Hardware |
| Embodiment | Single Chip |
| Vendor | Analog Devices, Inc. · website |
| Hardware versions | 1.00 |
Module description
The Sypher AES-256-bit Encryption FPGA Module provides secure traffic communication to Axnes' Polycon Next Generation (PNG) wireless intercom radio systems (MP50 PNG Transceiver and BST50 Base Station).
Security level exceptions
- Cryptographic Module Ports and Interfaces: Level 3
- Design Assurance: Level 3
- Mitigation of Other Attacks: N/A
Approved algorithms
| Algorithm | CAVP certificate |
|---|---|
| AES | 5177 |
Tested configurations
- Microsemi IGLOO2 FPGA
Validation history
| Date | Type | Lab |
|---|---|---|
| 2018-06-15 | Initial | atsec information security corporation |
| 2018-07-13 | Update | atsec information security corporation |
Status timeline
As observed by this tracker's snapshots. NIST publishes no dates for list moves; observation began 2026-08-21, so earlier changes carry no date.
- 2026-08-21: first observed by this tracker, status historical
- Validation dates on record: 2018-06-15, 2018-07-13